The present invention is related to a system for the manufacture of a substrate having a circuit pattern, such as a semiconductor device or liquid crystal display; and, more particularly, the invention relates to technology for inspecting a substrate pattern during fabrication.
Conventional optical or electron beam pattern inspection systems are described in Japanese Patent Laid-open No. H5-258703 and Japanese Patent Laid-open No. H11-160247.
FIG. 1 shows the constitution of a system disclosed in Japanese Patent Laid-open No. H5-258703 as an example of an electron beam pattern inspection system. In this system, an electron beam 2 from an electron beam source 1 is deflected in the X direction by a deflector 3 and is irradiated onto a target substrate 5 via an object lens 4, while a stage 6 is simultaneously made to move continuously in the Y direction. Secondary electrons 7 from the target substrate 5 are detected by a detector 8, and the detected signal is converted from analog to digital by an analog-to-digital (A/D) converter 9 to form a digital image, which is compared in an image processing circuit 10 to a digital image of a place that can be expected to be the same as the original, a place that differs is detected as a pattern defect 11, and the location of the defect is established.
FIG. 2 shows the constitution of the system disclosed in Japanese Patent Laid-open No. H11-160247 as an example of an optical inspection system. In this system, a light from a light source 21 is irradiated onto a target substrate 5 via an object lens 22, and a reflected light is detected by an image sensor 23 at that time. By repeatedly detecting the reflected light while a stage 6 moves at a constant speed, an image is detected as a detected image 24, and this image 24 is stored in memory 25. The detected image 24 is compared with a memory stored image 27, which can be expected to have the same pattern as the detected image 24, and if the patterns are identical, the detected image 24 is determined to be a normal portion. However, but if the patterns differ, this difference is detected as a pattern defect 11, and the defect location is established.
As an example, FIG. 3 shows a layout of a wafer 31 which represents a target substrate 5. Dies 32, which are ultimately cut apart to yield individual products of the same variety, are formed on wafer 31. Stage 6 is moved along a scanning line 33, and an image of the stripe region 34 is detected. When the present detection location A is at 35, an image of detection location B 36 in memory 25 is extracted as a stored image 27, and the two images are compared. Thereby, detection location A 35 is compared against a pattern that can be expected to be an identical pattern. Here, memory 25 possesses a capacity capable of holding an image that can be expected to be an identical pattern, that is used repeatedly in a ring shape to form an actual circuit.
In the case of both inspection systems, to confirm the results of the inspection, the inspected data is outputted to a review system. Thereafter, the wafer is transferred to and set on a table of the review system to review defects detected by the inspection system. In the review system, the defect to be reviewed is placed in a viewing field of the review system by using the inspected data outputted from the inspection system. Then, the image is visually observed to judge whether or not it has an actual defect or to infer what could have caused it. In such a reviewing method, a vast amount of image data acquired during the inspection is not effectively used.